Packet-switched and cell-switched networks use switch nodes to provide a shared transmission path for a multiplicity of ports, thereby reducing the overall cost and complexity of the ports and the network. A port may be coupled to a trunk such as an OC3 line for communicating to another switch node. Alternatively, a port may be coupled to an endpoint of a network such as customer premise equipment (CPEs).
FIG. 1 shows a prior art switch node 100 that comprises switch module 105 and port modules 110, 115, 120, and 125. Switch module 105 functionally operates as an N.times.N switching fabric having N inputs and N outputs. Therefore, for the example of N=4, switch module 105 is connected to port module 110 via input line 111 and output line 114, to port module 115 via input line 116 and output line 119, to port module 120 via input line 121 and output line 124, and to port module 125 via input line 126 and output line 129.
Port modules 110, 115, 120, and 125 use switch module 105 as a common interconnect for switching data packets between one another. The throughput of a switch module output is limited to the throughput of an output line, which typically results in only one packet being switched per output per transaction or "connection" cycle of switch module 100. Therefore, output or "port" contention arises when multiple port modules attempt to simultaneously transmit packets to the same destination port. Because only one packet may be switched to the destination port per connection cycle, the other packets are "blocked," and data loss can occur.
Packet buffering is typically performed to prevent the loss of blocked packets. For example, each of the port modules of switch node 100 includes input buffers to prevent packet loss due to contention for the same destination port module. Input buffers 112, 117, 122, and 127 are shown as first in first out buffers (FIFOs) and store all packets that are to be switched in a first-in-first-out manner, regardless of their destination port. Switch node 100 is said to use "input buffering" because packets are buffered by the port modules before they enter the switching fabric of switch module 105.
Input buffering allows switch module 105 to operate at the input line speed, which reduces the complexity and cost of switch module 105; however, the throughput of the switch node may be significantly reduced if port contention occurs. When a packet or cell at the head of a FIFO must wait for transmission, all subsequent packets in the FIFO must also wait even though their destination ports may be available during the present connection cycle. This phenomenon is called "head-of-line blocking."
An alternative switch node architecture uses output buffering to provide improved performance relative to input buffered switch nodes. FIG. 2 shows a prior art switch node 200 that uses output buffering and comprises switch module 205 and port modules 210, 215, 220, and 225. Switch module 205 functionally operates as an N.times.N switch matrix. Therefore, for the example of N=4, switch module 205 is connected to port module 210 via input line 211 and output line 214, to port module 215 via input line 216 and output line 219, to port module 220 via input line 221 and output line 224, and to port module 225 via input line 226 and output line 229. To guard against data loss due to output contention, switch module 205 includes output buffers associated with each of the port modules. Output buffers 212, 217, 222, and 227 are shown as FIFOs, but they may be implemented using a shared memory architecture.
Output buffering eliminates the head-of-line blocking effect of input buffered switch nodes. The primary drawback of an output buffered switch node is that switch module 205 must be operated N times faster than the input line speed, which significantly increases the complexity and cost of switch module 205 when compared to switch module 105 of input buffered switch node 100. For example, output buffering according to the prior art typically requires that output buffers be placed on the switch module because each output line only allows one packet to be passed to a port module per connection cycle wherein up to N-1 packets may be received for transfer per connection cycle. The output buffers must operate at the speed of the switch module 205, and memory costs are therefore significantly increased when compared to the memory costs for input buffering.